1. Field of the Invention
The present invention relates to a semiconductor device and a method of generating a sense signal, and more particularly, to a semiconductor device with a high-precision cascode connection and a method of generating a sense signal.
2. Description of the Related Art
Semiconductor memories are categorized into a volatile type in which information is lost by power off and a non-volatile type in which information is retained even by power off. The latter type of semiconductor memory is typically a flash memory in which data can be erased on a given-area basis with a reduced rewriting time. A cascode circuit is employed to implement the current-to-voltage conversion in the flash memories.
FIG. 1 is a diagram of a conventional cascode circuit. Referring to FIG. 1, the conventional cascode circuit 1 includes a pair of transistors 2 and 3, a resistor 4 for amplification, and a transistor 5. The paired transistors 2 and 3, which are cascode-connected, and the resistor 4, which is a pull-up cascode element, define a data line voltage DATAB, which is the drain voltage of the cell at the time of read. The cascode circuit 1 generates a sense amplifier input voltage Sain that depends on the current flowing through the cell selected by the selected activated word line.
FIG. 2 shows amplifying of the sense amplifier input voltage in the conventional cascode circuit. Part (a) of FIG. 2 shows a connection of the cascode circuit shown in FIG. 1 and a memory cell from which data is read, and part (b) thereof is a simplified version of part (a). In FIG. 2(a), reference numerals 6 and 7 indicate transistors, and a reference numeral 8 indicates a memory cell.
In the conventional cascode circuit 2, the sense amplifier input voltage Sain is qualitatively defined by (VCC-I-RL), as shown in FIG. 2. Thus, the amplitude of the sense amplifier input voltage Sain is limited to the range of the data line voltage DATAB to the power supply voltage VCC, namely, (VCC–DATAB). Two means are conceivable for obtaining the sense amplifier input voltage Sain having a large amplitude with the cascode circuit 1. The first means is to raise the power supply voltage VCC, and the second means is to reduce the data line voltage DATAB.
However, the power supply voltage VCC tends to be decreased in terms of reduction in power consumption. Thus, there is a difficulty in raising the power supply voltage VCC. On the other hand, reduction of the data line voltage DATAB certainly increases the amplitude of the sense amplifier input voltage Sain. However, the voltage of the bit line connected to the cell is also reduced. Therefore, there is a limitation on reduction of the data line voltage DATAB within the range in which a sufficiently responsible current is ensured during the sensing period.
A multi-bit cell is employed from requirements for a larger capacity of the non-volatile memory devices. Multi-bit data is stored in the multi-bit core cell, which can store information described by multiple bits. Hence, the cost per bit can be reduced. The multiple levels described by multi-bits are implemented by a reduced current margin, which is the difference between the read current of the core cell and a reference current that flows through a reference cell, as compared to the conventional SLC (Single Level Cell). In the future, the current margin will decrease as the number of multiple levels increases. Although repetitively described, the lower the power supply voltage, the smaller the current margin.
Reference is made to Patent Document 1: Japanese Patent Application Publication No. 9-171697, Patent Document 2: Japanese Patent Application Publication No. 11-120777, and Patent Document 3: Japanese Patent Application Publication No. 2001-250391.
Patent Document 1 describes a method of supplying the reference cell as the gate voltage of the transistor of the core cell. However, the reference voltage is affected by the gate of the core cell transistor and interconnection lines. It is thus difficult to match the reference circuit and the core cell circuit. Patent Document 2 describes a proposal about a comparator circuit used for multi-bit core cells. However, this proposal does not efficiently utilize the amplitude range of the power supply voltage, and is not capable of realizing a circuit operable with a low power supply voltage.
Patent Document 3 shows the reference voltage supplied as the gate voltage of the core cell transistor. However, the reference voltage applied to a differential amplifier and the gate voltage are short-circuited, and is likely to be affected by the gate of the core cell transistor and interconnection lines. This makes it difficult to match the reference side and the core side.
The present invention has an object of solving the above-mentioned problems of the conventional art and providing a semiconductor device with a high-precision cascode circuit capable of easily making a circuit match and operating with a low power supply voltage.